1. Field of the Invention
The invention relates to a device and to a method for exchanging data between memory controllers.
2. Description of the Related Art
From a cost and power point of view, the throughput between processor and memory is one of the most limited resources in a conventional computer. Virtualization, I/O processing (I/O; Input/Output), parallel processing, checkpointing and other techniques require memory operations with significant processing, such as memory-to-memory copying.
In conventional computer systems, since memory is exclusively connected to the processor or processor chip, these operations occupy processor-to-memory bandwidth. In past systems, the detailed operations of the memory, e.g. bank open, read, write, refresh, are controlled by the memory controller on the processor chip.
However, in upcoming conventional systems, the memory controller is moved into a separate chip that may be integrated with the memory chip on Dual Inline Memory Modules (DIMM). This may allow a more autonomous operation of the memory.
Typically, if several memory modules are present in one system, the memory modules are used in an interleaved way. This offers a good balancing over the memory channels when continuous addresses are accessed. This address assignment scheme rules out most memory operations carried out locally on one memory module only. For instance, if a list needs to be traversed, e.g. queues of an I/O device in virtual memory, the list elements would be distributed over several memory modules.
For example, FIG. 8 shows a schematic block diagram of a conventional device 800 for exchanging data between memory controllers 801 and 802. Each memory controller 801, 802 is coupled to a memory 803, 804. Further, each memory controller 801, 802 is coupled to a processor 805, 806 or processor chip. The processors 805, 806 are coupled to each other. If the memory controller 801 wants to exchange data with the memory controller 802, it has to transmit the data over the processors 805 and 806.
Further, an I/O device 807 may be a part of the device 800. For example, the I/O device 807 can be coupled to the processor 805. If the I/O device 807 wants to write into a memory, for example memory 803, it has to transmit the data over the processor 805.
Thus, the processor-to-memory bandwidth is limited in any case of transmitting data between the memory controllers 801 and 802.
Accordingly, it is an aspect of the present invention to improve the exchange of data between memory controllers.